The following is a two-part article by Mike James that appeared in Electronics and Computing Monthly in April and May, 1985. They described the circuit diagram of the BBC Micro Model B. A quick Google suggests that these documents are not available elsewhere on the web, so I preserve them here for posterity.
Yes – I really am sad enough that I still find these documents an interesting read, some 22 years after they were first published. Hopefully someone else will find this material interesting – perhaps even useful. If that someone is you, please leave me a comment. It would encourage me enormously to know that I am not the only sad old geek that has fond memories of simpler days.
This reproduction of these articles was achieved by quickly hand-correcting an OCR of a poor and aging photocopy (I never did have the originals). As a result, it is likely to contain numerous typos that were not present in the original. Unfortunately, several of the sub-titles were impossible to read in the photocopy in the first article, so I have guessed the missing words and marked them with ‘<’ and ‘>’. The circuit diagram itself, whilst readable in the photocopy, is unlikely to scan very well using my poor equipment. Fortunately, this diagram is already available elsewhere on the web.
Part 1 is reproduced from Electronics and Computing Monthly, April 1985, pages 33-34.
The Diagram Diagnosed
Mike James makes a careful study of the BCC micro’s circuit diagram (printed on our centre pages) and finds it still one of the most innovative designs around.
The BBC Micro is still one of the most innovative microcomputer designs from both the software and the hardware point of view. The internal design of the BBC’s software has been the subject of a number of articles in E&CM and it is the purpose of this article to redress the balance in favour of the hardware.
When contemplating the BBC Micro’s hardware it is all too easy to go on at length about its ‘larger’ features such as the Tube or its ability to page ROMs but the machine is also interesting at a more detailed level. If you examine its circuit diagram it is not long before you spot some additional clever aspects of the design. Sometimes it is simply the way a timing signal has been derived, or something to do with the way the different parts of the hardware work together. Reading circuit diagrams is not often a rewarding experience but in the case of the BBC Micro it certainly is! To help get you started the following notes provide a general overview of each section of the circuit and highlight a few of the special features. Throughout it is assumed that you are a BBC Micro user, know something about computer design, have a TTL data book and have or can acquire data sheets on the other chips in the design.
Timing, CPU <and> Address <Decoding>
The BBC Micro uses a wide range of clock pulses to synchronise its operation. Although the 6502 CPU (IC 1) is a double speed device running at 2MHz, the system’s dynamic RAM is accessed four times in every microsecond; twice by the 6502 and twice by the 6845 CRTC (Cathode Ray Tube Controller). Thus the RAMs are cycled at 4MHz. A 16MHz crystal oscillator (IC43 and IC40) provides the master clock that is divided down by the video ULA (IC6) to 8, 4 and 1MHz (all in phase). A 2MHz clock for the 6502 is provided by IC30 by phase shifting the original 2MHz clock from lC6. As some of the peripherals that the 6502 has to access to are single speed devices IC33, IC31 and IC34 are used to stretch the clock to 1MHz when an appropriate address is detected by IC23. A 6MHz clock is generated by IC40, IC38 and IC37 for use by the teletext character generator IC5.
A power on reset signal is generated by a 555 timer (IC16) and a simple RC network (R20 and C10). The reset signal from the RC network is only applied to the system 6522 VIA (IC3). The 555 can also be triggered by a reset switch (which is not normally fitted to the main PCB) or by the BREAK key on the keyboard. Thus, by examining the state of the system VIA, the machine can discover if a reset is due to power on. Obviously following power on there is no valid data in memory but after the reset button is pressed there may well be.
The CPU’s address bus is distributed around the rest of the circuit but individual chip select signals are derived by IC20, IC21, IC22, IC24, IC25, IC26 and IC29. Chip selects for the Tube, A to D, Econet interface, floppy disc controller and the two VIAs are provided by IC24 (which uses IC22 as a high address detector). Two of the outputs of IC24 are further decoded by IC26 to provide further chip selects for the Econet station number register, the ROM select latch, the video ULA, the serial ULA, the 6850 ACIA and the CRTC. Notice that the R/W line is used in the decoding of these first four select lines which means that it is only possible to write to the ROM select latch and to read the station lD(entifier) – that is they both occupy the same address – and it is only possible to write to the video ULA. The address decoding for the ROMs is straightforward apart from the use of IC76 to select which of the four paged ROMs is used. The expansion I/O areas Fred and Jim are selected by outputs from IC20. The RAM is selected by simply using address line 15 to indicate accesses in the lower 32K. A signal for slow (1 MHz) devices is derived by IC23.
The BBC Micro’s 32K of RAM is provided by sixteen 4816 dynamic RAM chips – IC53 to IC68. As already mentioned these are accessed four times every microsecond and this implies that they are very fast devices. The row and column addresses are supplied by six octal butlers IC8 to IC13. The CPU accesses the RAM via IC12 and IC13 and the CRTC via IC8 to IC11. Which device has access is controlled by IC45. The dynamic RAM is refreshed by the CRTC continually cycling through all of the possible row addresses. The data bus to the CPU and other devices is buffered by IC14.
Perhaps the cleverest part of the entire BBC Micro’s circuit is the way that the 6845 CRTC is used. If you look at an application sheet for the 6845 you will see that it is supposed to access two different types of memory. An area of RAM, used to store ASCII codes and an area of ROM to generate the dot patterns of the characters to be displayed. The idea is that the output of the RAM is used to select a dot pattern from the ROM and the CRIC provides extra addressing to select each byte of data which make up the characters. Of course the BBC Micro (in modes 0 to 6) doesn’t use a ROM to generate the dot patterns as they are stored directly in RAM. Another interesting feature is the way that the 6845 is coaxed into providing colour information – the raw 6845 is a monochrome device. The key to understanding how the 6845 has been used in the BBC Micro is to notice that although its address lines are segregated into two groups – MA0 to MA13 and RA0 to RA2 – they can just as easily be used to address a single block of memory. In other words, the CRTC simply addresses the memory a certain number of times per TV scan line and what happens to the data that is produced is not its concern.
Once the data has been selected by the CRTC it is sent (a byte at a time) to the video ULA (IC6) where it is serialised and applied as the address to a small area of static RAM – the palette RAM. This is responsible for adding the colour to the display. The output of the palette RAM is a four bit word indicating the state of the R(ed), G(reen), B(lue) and Flash signals. The RGB signal is fed (via Q4 to Q6) to the RGB monitor connector and to the PAL colour encoder formed by Q10, IC46, IC47, IC48, Q8 and Q9. The PAL signal is finally applied to a standard ASTEC UHF modulator and brought out through a phono socket. A composite monochrome video signal is also provided by Q7 and Q8 for monochrome monitors. Notice that all the TV sync signals are generated by the CRTC. The cursor signal is mixed into the video signal by the video ULA.
There is one graphics mode where the CRTC is almost used as its makers intended – Mode 7. In this mode the CRTC addresses the top 1K of RAM to obtain ASCII codes that are applied to a teletext character generator – IC5. Even here however there are some tricky methods used. CRTC address line MA13 is used as a teletext indicator and this is used to select between two pairs of octal buffers that apply the rest of the CRTC’s address lines to the RAM. Modes 0 to 6 use octal buffers IC8 and IC9 and Mode 7 use IC10 and IC11. The reason for this is that the CRTC’s row address lines are not applied to the teletext ROM and so the same ASCII data has to be presented to it more than once. This implies using a different addressing scheme for the RAM and this is accomplished by using two sets of buffers. The RGB output of the Teletext ROM is applied to three input lines of the video ULA and hence on to the rest of the video circuitry.
The time it takes to scroll a screen increases with the amount of memory involved. As the BBC Micro uses up to 20K of memory for a display, simple software scrolling would take rather a long time. To speed things up a little a very ingenious system of hardware scrolling is used. The CRTC contains a register that holds the address of the first character that will be displayed. It is obvious that a scroll can he achieved simply by incrementing the value in this register by the number of memory locations used to store a line of text. The only trouble is that the area of memory addressed will go beyond the 32K RAM limits. Addresses that are above the 32K limit should obviously be reduced to refer to the start of the display area. This can be done by adding a constant to the address that the CRTC generates. The constant is generated by IC37, IC36 and IC40 from the two lines C0 and C1 that indicate the currently selected display mode. The constant is added to four of the high order address lines generated by the CRTC by 1C39.
The System VIA
The CA1 input is used to interrupt the processor if any key on the keyboard is pressed, the CA2 input is used to signal the start of a new TV frame, the CB1 input signals the end of an A to D conversion and finally the CB2 input is used to interrupt the processor in response to a pulse from a lightpen.
The rest of the VIA’s I/O lines are best thought of as forming a sort of auxiliary peripheral data and address bus. The eight A side data lines are used as a bi-directional data bus between the processor and a number of other chips (including the keyboard and sound generator). The first four B side data lines are used as an ‘address bus’ to select or activate a number of devices. This is achieved by use of an addressable latch (IC32). The first three B side data bits, PB0 to PB2, are used to address a location in the latch and PB3 is used to set the state of the location. (The latch is clocked by IC31). In this way four VIA lines can be used to set the state of the eight outputs of the latch! Bit zero of the latch enables the sound chip (IC18), bits one and two control the speech chip (when fitted), bit three enables the keyboard, bits four and five provide the signals C0 and C1 used to indicate the mode during hardware scrolling and bits six and seven control the caps lock and shift lock LEDs on the keyboard. The remaining B side data lines are configured as inputs. PB4 and PB5 are used to detect the state of the ‘fire buttons’ on the joystick interface and PB6 and PB7 are status inputs from the speech synthesiser.
CONTINUED NEXT MONTH
Part 2 is reproduced from Electronics and Computing Monthly, May 1985, page 58.
The Diagram Diagnosed
Mike James concludes his voyage around the BBC micro’s circuit diagram with a desription of the various I/O facilities offered by the computer.
The analogue port provided by the A to D converter chip (IC73) is very simple. Its data and control registers are connected to the system data bus and its address is decoded by IC24 as already described. The end of conversion signal is connected to CB1 of the system VIA. Thus conversion consists of writing data to the control register, waiting for the end of conversion signal and then reading the data. The only point worth noting is the need to derive separate read and write strobes for this chip, a task undertaken by IC77 in the disk controller circuit. Problems and solutions to the instability of the voltage reference provided by DB6 to DB8 have already been described in F&CM a number of times.
The sound chip, IC18, is interfaced to the system via the slow data bus provided by the A side of the system VIA. (Notice that tins means that the sound chip doesn’t appear in the BBC Micro’s memory map.) The sound chip is selected by the addressable latch as already described. Analogue processing is provided by IC17 and IC19. Notice that there is a volume control (VR1) just before the final stage of amplification.
Cassette and Serial IO
The cassette and serial interface is provided mainly by the serial ULA IC7 and a standard 6850 ACIA IC4. The ACIA is connected to the system data bus and is selected by IC26 as described earlier. What is interesting about tins configuration is the way that the ULA takes the signals from the ACIA and sends them to provide a cassette interlace. The serial ULA contains a baud rate generator, tone detector, data separator and a sine wave synthesiser. This combination provides a sophisticated serial interface (with software programmable baud rates) and a very reliable cassette interface. When writing to the cassette the serial data from the ACIA simply controls the frequency produced by the sine wave generator in the serial ULA. When reading data from the cassette, the data separator changes the audio tones into a serial data stream and a clock signal. The serial data stream is applied to the serial input of the ACIA and the clock pulses to the receive clock input. In this way the data recovery from the cassette is very tolerant of speed fluctuations. The analogue side of the circuit is composed of IC35 and two transistors Q1 and Q2. The cassette motor is controlled by a small relay driven by Q3. The signal side of the RS423 interface is provided by IC74 and IC75.
The User VIA & 1MHz Bus
The second VIA in the system is dedicated to providing an eight-bit user port and a standard Centronics printer interface. It is connected to the system data bus and it is selected by IC24. The printer port is formed from the A side data lines, buffered by IC70 and CA1 and CA2 for handshaking. Notice that CA2 is buffered by IC27 and a transistor (Q11) to increase its current drive capability. The user port is provided by all of the B side lines PB0 to PB7 and CB1 and CB2. Notice that the user port is not buffered in any way and therefore has limited current drive. On the plus side the lack of buffering means that any data line in the user port can be used for input or output as desired.
“…Understanding circuit operation is rewarding…”
The 1MHz bus provides a fully buffered (IC71) subset (A0 to A7) of the system address bus and a fully buffered (IC72) copy of the system data bus. Two additional select lines are provided by IC20 for the Fred and Jim I/O areas. Using these selects and the eight address lines two 256 byte I/O areas can be created – one from FC00 and one from FD00. The only other signal on the 1MHz bus worth a mention is the analogue input which is mixed with the output of the sound generator by a resistive mixer following IC17.
The Tube is another interface bus like the 1MHz bus but in this case it is not buffered in any way. A full copy of the data bus and lines A0 to A7 of the address bus is provided. In normal operation only 32 bytes of address space are allocated to the Tube but it is possible to disable a section of OS ROM (IC51) so that the Tube can make use of its full 256 byte addressing range.
The keyboard is interfaced to the rest of the system by the system VIA (IC3) but for most of the time it is ‘free running’. In free running mode a four-bit counter (IC1k) is clocked at 1MHz and its output is applied to a one of sixteen selectors (IC3k). In this way each column lime of the keyboard is made active in turn. Any keypresses short a column line to a row line and this event is detected by IC4k which sends a signal to the system VIA which then causes and interrupt. Following a keyboard interrupt the free running mode is stopped and the keyboard handling software causes the processor to load column numbers directly into the four bit counter and row numbers directly into a one of eight selector (IC2k).
…The BBC micro is still one of the most innovative micro computer designs…
In this way the processor can test each key in turn to discover if it is pressed or not. (A pressed key will connect a row and column and when this combination is tested a pulse will be sent to the system VIA by IC4k).
Three areas of the BBC Micro’s circuit mayo not been described – the disk interface, the speech synthesiser and the Econet interface. Each of these is almost a complete system in itself and as such is beyond the scope of this introduction. However they are included in tine circuit diagram and if you know how they are used you should have no trouble in following the way that they fit into the rest of the system.
All areas of tine circuit that have been covered have only been done so very briefly. For a more detailed and leisurely discussion of the BBC Micro’s hardware (and software) see my book “The BBC Micro: an expert guide” published by Granada (1983).